View DM9101_1117322.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DM9101 10/100mbps ethernet physical layer single chip transceiver final 1 version: DM9101-ds-f03 july 22, 1999 general description the DM9101 is a physical-layer, single-chip, low-power transceiver for 100base-tx, and 10base-t operations. on the media side, it provides a direct interface either to unshielded twisted pair category 5 cable (utp5) for 100base-tx fast ethernet, or utp5/utp3 cable for 10base-t ethernet. through the ieee 802.3u media independent interface (mii), the DM9101 connects to the medium access control (mac) layer, ensuring a high inter- operability among pr oducts from di fferent vendors. the DM9101 uses a low-power and high-performance cmos process. it contains the entire physical layer functions of 100base-tx as defined by ieee 802.3u, including the physical coding sublayer (pcs), physical medium attachment (pma), 100base-tx twisted pair physical medium dependent sublayer (tp-pmd), and a 10base-t encoder/decoder (enc/dec). the DM9101 provides strong support for the auto-negotiation function utilizing automatic media speed and protocol selection. the DM9101 incorporates an internal wave-shaping filter to control rise/fall time, eliminating the need for external filtering on the 10/100mbps signals. patent-pending circuitry includes: smart adaptive receiver equalizer digital algorithm for high frequency clock/data recovery circuit high speed wave-shaping circuit block diagram mii signals mii interface/ control 4b/5b encoder 4b/5b decoder register code- group alignment descrambler serial to parallel nrzi to nrz rx crm mlt-3 to nrzi adaptive eq digital logic scrambler parallel to serial nrz to nrzi nrzi to mlt-3 mlt-3 driver rise/fall time ctl tx cgm led driver collision detection carrier sense auto- negotiation 10base-t module rx tx 125m clk 25m clk led1-4# 25m osci rxi+/- rxi+/- 10txd+/- 100txd+/-
DM9101 10/100mbps ethernet physical layer single chip transceiver 2 final version: DM9101-ds-f03 july 22, 1999 table of contents general description ................................................1 block diagram ........................................................1 features .................................................................3 pin configuration: DM9101e lqfp .........................3 pin configuration: DM9101f qfp ...........................4 pin description .......................................................5 functional description mii interface ......................................................12 100base-tx operation ......................................14 100base-tx transmit ........................................14 100base-tx operation ......................................15 4b5b encoder ...................................................15 scrambler..........................................................15 parallel to serial converter ................................15 nrz to nrzi encoder ........................................15 mlt-3 converter ...............................................15 mlt-3 driver .....................................................15 4b5b code group .............................................16 100base-tx receiver ........................................17 signal detect .....................................................17 digital adaptive equalization ..............................17 mlt-3 to nrzi decoder .....................................17 clock recovery module .....................................18 nrzi to nrz .....................................................18 serial to parallel ................................................18 descrambler......................................................18 code group alignment ......................................18 4b5b decoder ...................................................18 10base-t operation ..........................................18 collision detection.............................................18 carrier sense ....................................................18 auto-negotiation ................................................18 mii serial management ......................................19 serial management interface .............................19 management interface ? read frame structure .19 management interface ? write frame structure.19 register description .............................................20 - key to default....................................................20 basic mode control register (bmcr) - register 0...........................................................21 basic mode status register (bmsr) - register 1...........................................................22 phy id identifier register #1 (phyidr1) - register 2 .......................................................... 23 phy id identifier register #2 (phyidr2) - register 3 .......................................................... 24 auto-negotiation advertisement register (anar) - register 4 .......................................................... 24 auto-negotiation link partner ability register (anlpar) - register 5 ......................................... 25 auto-negotiation expansion register (aner) - register 6 .......................................................... 26 davicom specified configuration register (dscr) - register 16......................................................... 26 davicom specified configuration and status register (dscsr) - register 17 ........................... 28 10base-t configuration / status (10btscrcsr) - register 18......................................................... 29 absolute maximum ratings .................................. 30 dc electrical characteristics ................................ 31 ac characteristics ................................................ 32 timing waveforms mii-100base-tx transmit timing diagram ........ 33 mii-100base-tx receive timing diagram ......... 33 auto-negotiation and fast link pulse timing ..... 34 mii-10base-t transmit timing diagram ............ 35 mii-10base-t receive nibble timing diagram .. 35 10base-t sqe (heartbeat) timing diagram ..... 36 10base-t jab and unjab timing diagram ........ 36 mdio timing when output by sta ................ 37 mdio timing when output by DM9101 .......... 37 magnetics selection guide ................................... 38 crystal selection guide ........................................ 38 application circuit (for reference only) .................. 40 package informatio n............................................. 41 ordering information............................................. 42 company overview .............................................. 42 contact windows .................................................. 42
DM9101 10/100mbps ethernet physical layer single chip transceiver final 3 version: DM9101-ds-f03 july 22, 1999 features ? 10/100base-tx physical-layer, single-chip transceiver ? compliant with ieee 802.3u 100base-tx standard ? compliant with ansi x3t12 tp-pmd 1995 standard ? compliant with ieee 802.3u auto-negotiation protocol for automatic link type selection ? supports the mii with serial management interface ? supports full duplex operation for 10 and 100mbps ? high performance 100mbps clock generator and data recovery circuitry ? adaptive equalization circuitry for 100mbps receiver ? controlled output edge rates in 100mbps ? supports a 10base-t interface without the need for an external filter ? provides loop-back mode for system diagnostics ? includes flexible led configuration capability ? digital clock recovery circuit using advanced digital algorithm to reduce jitter ? low-power, high-performance cmos process ? available in both a 100 pin lqfp and a 100 qfp package pin configuration: DM9101e lqfp 36 DM9101e 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 8 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6 1 60 59 58 57 56 55 54 53 52 5 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 nc avcc agnd agnd 10btser bpscr bp4b5b bpalign rptr/node# opmode3 opmode2 opmode1 opmode0 phyad4 phyad3 dvcc dgnd phyad2 phyad1 phyad0 testmode reset# rx_en rx_er/rxd4 rx_dv 26 27 28 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 tx_er/txd4 col crs rx_clk dvcc dgnd rxd0 rxd1 rxd2 rxd3 dvcc dgnd mdio mdc tx_clk tx_en dvcc dgnd txd0 txd1 txd2 txd3 txled# rxled# linkled# nc nc nc agnd avcc avcc rxi- rxi+ agnd agnd 10txo- 10txo+ avcc avcc agnd agnd nc nc avcc avcc agnd agnd 100txo- 100txo+ avcc avcc osci/x1 x2 agnd osc/xtl# avcc agnd bgref bgret dgnd dgnd dgnd dvcc tridrv utp speed10 rx_lock dgnd nc linksts clk25m dvcc fdxled# colled# dgnd
DM9101 10/100mbps ethernet physical layer single chip transceiver 4 final version: DM9101-ds-f03 july 22, 1999 pin configuration: DM9101f qfp avcc nc nc nc nc agnd avcc rxi- rxi+ agnd 10txo- agnd avcc avcc agnd agnd nc nc avcc agnd agnd 100txo- 100txo+ avcc osci/x1 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rx_en rx_er/rxd4 rx_dv col crs rx_clk dvcc dgnd rxd0 dvcc mdc tx_clk dgnd txd0 txd1 txd2 txd3 tx_er/txd4 txled# rxled# linkled# dgnd colled# 50 49 48 47 46 45 44 43 42 40 41 39 38 37 36 35 34 33 32 31 fdxled# dvcc clk25m linksts nc dgnd rx_lock speed10 utp tridrv dvcc dgnd dgnd dgnd bgret bgref agnd avcc osc/xtl# agnd 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 agnd agnd opmode0 opmode1 opmode2 reset# testmode DM9101f 10txo+ phyad0 phyad1 dgnd dvcc phyad3 phyad4 opmode3 rptr/node# bpalign bp4b5b bpscr 10btser avcc dvcc tx_en mdio dgnd rxd3 rxd2 rxd1 phyad2 avcc
DM9101 10/100mbps ethernet physical layer single chip transceiver final 5 version: DM9101-ds-f03 july 22, 1999 pin description pin no. pin name i/o description lqfp qfp mii interface 54 56 tx_er/ txd4 i transmit error: in 100mbps m ode, if this signal is asserted high and tx_en is active, the halt symbol is substituted for the actual data nibble. in 10mbps mode, t his input is ignored. in bypass modes ( bp4b5b or bpalign), tx_er becomes the txd4 pin, the fifth txd data bit. 55-58 57 - 60 txd3 txd2 txd1 txd0 i transmit data: transmit data input pins for nibble data from the mii in 100mbps or 10mbps nibble mode (25 mhz for 100mbps mode, 2.5mhz for 10mbps nibble mode). in 10mbps se rial mode, the txd0 pin is used as the serial data input pin. txd[3:1] are ignored. 61 63 tx_en i transmit enable: active high input indicates the presence of valid nibble data on txd[3:0] for both 100mbps or 10mbps nibble mode. in 10mbps se rial mode, active high indi cates the presence of valid 10mbps data on txd0. 62 64 tx_clk o,z transmit clock: transmit clock output from the DM9101: - 25mhz nibble transmit clock derived from transmit phase locked loop(tx pll) in 100base-tx mode - 2.5mhz transmit clock in 10base-t nibble mode - 10mhz transmit clock in 10base-t serial mode 63 65 mdc i management data clock: synchronous clock to the mdio management data input/output serial interface which is asynchronous to transmit and receive clocks. the maximum clock rate is 2.5mhz. 64 66 mdio i/o management data i/o: bi-directional management instruction/data signal that may be driven by the station management entity or the phy. this pin requires a 1.5k ? pull-up resistor. 67-70 69 - 72 rxd3 rxd2 rxd1 rxd0 o,z receive data: nibble wide receive data (synchr onous to r x_clk - 25mhz for 100base-tx mode, 2.5mhz for 10base-t nibble mode). data is driven on the falling edge of rx_clk. in 10mbps se rial mode, the rxd0 pin is used as the data output pin. rxd[3:1] are ignored. 73 75 rx_clk o,z receive clock: provides the recovered receive clock for different modes of operation: - 25mhz nibble clock in 100mbps mode - 2.5mhz nibble clock in 10mbps nibble mode - 10mhz receive clock in 10mbps serial mode
DM9101 10/100mbps ethernet physical layer single chip transceiver 6 final version: DM9101-ds-f03 july 22, 1999 pin description (continued) pin no. pin name i/o description lqfp qfp mii interface (continued) 74 76 crs o,z carrier sense: this pin is asserted high to indicate the presence of carrier due to receive or transmit activities in 10base-t or 100base-tx half duplex modes. in repeater, when full duplex or loop-back mode is a logic 1, it indicates the presence of carrier due only to receive activity. 75 77 col o,z collision detect: asserted high to indicate detection of collision conditions in 10mbps and 100mbps half duplex modes. in 10base-t half duplex mode with heartbeat set active (bit 13, register 18h), it is also asserted for a duration of approximately 1ms at the end of transmission to indicate heart beat. in full duplex mode, this si gnal is always logic 0. there is no heartbeat function in full-duplex mode. 76 78 rx_dv o,z receive data valid: asserted high to indic ate that valid data is present on rxd[3:0]. 77 79 rx_er/ rxd4 o,z receive error: asserted high to indicate that an invalid symbol has been detected inside a received packet in 100mbps mode. in a bypass mode (bp4b5b or bpalign modes), rx_er becomes rxd4, the fifth rxd data bit of the 5b symbols. 78 80 rx_en i receive enable: active high enabled for receive signals rxd[3:0], rx_clk, rx_dv and rx_er. a low on this input tri-states these output pins. for normal operation in a node application, this pin s hould be pulled high. media interface 7, 8 9, 10 rxi-, rxi+ i 100/10mbps differential input pair: these pins are the differential receive input for 10base-t and 100base-tx. they are capable of receiving 100base-tx mlt-3 or 10base-t manchester encoded data. 11, 12 13, 14 10 txo-, 10 txo+ o 10base-t differential output pair: this output pair provides controlled rise and fall times designed to filter the transmitters output. 23, 24 25, 26 100 txo-, 100 txo+ o 100base-tx differential output pair: this output pair drives mlt-3 encoded data to the 100m twisted pair interface and provides controlled rise and fall times des igned to filter the transmitter output, reducing any associated emi.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 7 version: DM9101-ds-f03 july 22, 1999 pin description (continued) pin no. pin name i/o description lqfp qfp led interface : these outputs can directly drive leds or provide status information to a network m anagement device. 48 50 fdxled# (polled) o polarity/full duplex led: indicates full duplex mode status for 100mbps and 10mbps operation (active low). if bit 4 of register 16 (fdxled_mode) is set, the fdxled# pin function will change to indicate the polarity status for 10mbps operation. if polarity is inverted, the polled will go on. 49 51 colled# o collision led: indicates the presence of c ollision activity for 10mbps and 100mbps operation. this led has no meaning for 10mbps or 100mbps full duplex operation (active low). 51 53 linkled# (traffic led) o link led: indicates good link status for 10mbps and 100mbps operation (active low). it functions as the traffic led w hen bit 5 of register 16 is set to 1. in traffic led mode, it is always on when the link is ok. the traffic led flashes when transmitting or receiving. 52 54 rxled# od receive led: indicates the presence of receive activity for 10mbps and 100mbps operation (active low). the DM9101 incorporates a "monostable" function on the rxled output. this ensures that even minimal receive activity will generate an adequate led on time. 53 55 txled# od transmit led: indicates the presence of transmit activ ity for 10mbps and 100mbps operation (active low). the DM9101 incorporates a "monostable" function on the txled output. this ensures that even minimal transmit activity will generate an adequate led on time. device configuration/control/status interface 40 42 utp o utp cable indication: utp=1: indicates utp cable is used. 41 43 speed10 o speed 10mbps: when set high, this bit indicates a 10mbps operation, when set low 100mbps operation. this pin can drive a low current led to indicate that 100mbps operation is selected. 42 44 rx_lock o lock for clock/data recovery pll: when this pin is high it indicates that the receiver recovery pll logic has locked to the input data stream. 45 47 linksts o link status register bit: this pin reflects the status of bit 2 register 1.
DM9101 10/100mbps ethernet physical layer single chip transceiver 8 final version: DM9101-ds-f03 july 22, 1999 pin description (continued) pin no. pin name i/o description lqfp qfp device configuration/control/status interface (continued) 88-91 90 - 93 opmode0 opmode1 opmode2 opmode3 i opmode0 - opmode3: these pins are used to control the forced or advertised operating mode of the DM9101 (see table below). the value is latched into the DM9101 registers at power-up/reset. opmode3 opmode2 opmode1 opmode0 function 0 0 0 0 auto-neg enable with all capabilities with flow control 0 0 0 1 auto-neg enable without all capabilities without flow control 0010auto-neg 100tx fdx with flow control only 0011auto-neg 100tx fdx/hdx without flow control 0 1 0 0 auto-neg 10tp fdx with flow control only 0 1 0 1 auto-neg 10tx fdx/hdx without flow control 0 1 1 0 manual select 100tx fdx 0 1 1 1 manual select 100tx hdx 1 0 0 0 manual select 10tx fdx 1 0 0 1 manual select 10tx hdx 92 94 rtpr/nod e# i repeater/node mode: when set high, this bit selects repeater mode; when set low, it selects node. in repeater mode or node m ode with full duplex configured, the carrier sense (crs) output from the DM9101 will be asserted only during receive activity. in node mode or a mode not configured for full duplex operation, crs will be asserted during receive or transmit activity. at power-up/reset, the value on this pin is latched into register 16, bit 11. 93 95 bpalign i bypass alignment: allows 100mbps transmit and receive data streams to bypass all of the transmit and receive operations when set high. at power-up/reset, the value on this pin is lat ched into bit register 16 ,bit 13.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 9 version: DM9101-ds-f03 july 22, 1999 pin description (continued) pin no. pin name i/o description lqfp qfp device configuration/control/status interface (continued) 94 96 bp4b5b i bypass 4b5b encoder/decoder: allows 100mbps transmit and receive data streams to bypass the 4b to 5b encoder and 5b to 4b dec oder circuits w hen set high at power-up/reset, the value on this pin is lat ched into register 16, bit 15. 95 97 bpscr i bypass scrambler/descrambler: allows 100mbps transmit and receive data streams to bypass the scrambler and descrambler circuits when set high. at power-up/reset, the value on this pin is lat ched into register 16, bit 14. 96 98 10btser i serial/nibble select: 10mbps serial operation: when set high, this input selects a serial data transfer mode. manchester encoded transmit and receive data is exchanged serially with a 10mhz clock rate on the least significant bits of the nibble-wide mii data buses, pin txd[0] and rxd[0] respectively. this mode is intended for use with the DM9101 connected to a device (mac or repeater) that has a 10mbps serial interface. serial operation is not supported in 100mbps m ode. for 100mbps, this input is ignored. 10 and 100mbps nibble operation: when set low, this input selects the mii compliant nibble data transfer mode. transmit and receive data is exc hanged in nibbles on the txd[3:0] and rxd[3:0] pins respectively. at power-up/reset, the value on this pin is lat ched into register 18, bit 10. clock interface 27 29 osci/x1 i crystal or oscillator input: this pin should be connected to a 25mhz ( 50 ppm) crystal if osc/xtl#=0 or a 25mhz ( 50ppm) external ttl oscillator input, if osc/xtlb=1. 28 30 x2 o crystal oscillator output: an external 25mhz ( 50 ppm) crystal should be conne cted to this pin if osc/xtl#=0, or left unconnected if osc/xtl#=1. 30 32 osc/xtl# i crystal or oscillator selector pin: osc/xtl#=0: an external 25mhz ( 50ppm) crystal should be connected to x1 and x2 pins. osc/xtl#=1: an external 25mhz ( 50ppm) oscillator should be connected to x1 and x2 sho uld be left unconnected. 46 48 clk25m o,z 25mhz clock output:. this clock is derived directly from the crystal circuit.
DM9101 10/100mbps ethernet physical layer single chip transceiver 10 final version: DM9101-ds-f03 july 22, 1999 pin description (continued) pin no. pin name i/o description lqfp qfp phy address interface: phyad[4:0] provides up to 32 unique phy address. an address selection of all zeros ( 00000) will result in a phy isolation condition. see the isolate bit description in the bmcr, address 00. 81 83 phyad0 i phy address 0: phy address bit 0 for multiple phy address applications. the status of this pin is latched into register 17, bit 8 during power up/reset. 82 84 phyad1 i phy address 1: phy address bit 1 for multiple phy address applications. the status of this pin is latched into register 17, bit 7 during power up/reset. 83 85 phyad2 i phy address 2: phy address bit 2 for multiple phy address applications. the status of this pin is latched into register 17, bit 6 during power up/reset. 86 88 phyad3 i phy address 3: phy address bit 3 for multiple phy address applications. the status of this pin is latched into register 17, bit 5 during power up/reset. 87 89 phyad4 i phy address 4: phy address bit 4 for multiple phy address applications. the status of this pin is latched into register 17, bit 4 during power up/reset. miscellaneous 1-3, 17, 18, 44, 100 2 - 5, 19, 20, 46 nc no connect: leave these pins unconnected (floating). 33 35 bgref i bandgap voltage reference: connect a 6.01k ? , 1% resistor between this pin and the bgret pin to provide an accurate current reference for the DM9101. 34 36 bgret i bandgap voltage reference return: return pin for 6.01k ? resistor connection. 39 41 tridrv i tri-state digital output pins: when set high, all digital output pins are set to a high impedance state, and i/o pins, go to input mode. 79 81 reset# i reset: active low input t hat initializes the dm 9101. it s hould remain low for 30ms after vcc has stabilized at 5vdc (normal) before it transitions high. 80 82 testmode i test mode control pin: testmode=0: normal operating mode. testmode=1: enable test mode.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 11 version: DM9101-ds-f03 july 22, 1999 pin description (continued) power and ground pins : the power (vcc) and ground (gnd) pins of the DM9101 are grouped in pairs of two cat egories - d igital circuitry power/ground pairs and analog circuitry power/ground pair. pin no. pin name i/o description lqfp qfp group a - digital supply pairs 35, 36, 37, 43, 50, 59, 65, 71, 84 37, 38, 39, 45, 52, 61, 67, 73, 86 dgnd p digital logic ground. group a - digital supply pairs ( continued) 38, 47, 60, 72, 66, 85 40, 49, 62, 74, 68, 87 dvcc p digital logic power supply group b - analog circuit supply pairs 4, 9, 10, 15, 16, 21, 22, 29, 32, 97, 98 6, 11, 12, 18, 17, 23, 24, 31, 34, 99, 100 agnd p analog circuit ground 5, 6, 13, 14, 19, 20, 25, 26, 31, 99 1, 7, 8, 15, 16, 21, 22, 27, 28, 33 avcc p analog circuit power supply
DM9101 10/100mbps ethernet physical layer single chip transceiver 12 final version: DM9101-ds-f03 july 22, 1999 functional description the DM9101 fast ethernet single-chip transceiver, provides the functionality as specified in ieee 802.3u, integrates a complete 100base-tx module and a complete 10base-t module. the DM9101 provides a media independent interface (mii) as def ined in the ieee 802.3u standard (clause 22). the DM9101 performs all pcs (physical coding sublayer), pma (physical media access), tp-pmd (twisted pair physical medium dependent) sublayer, 10base-t encoder/decoder, and twisted pair media access unit (tpmau) functions. figure 1 shows the major functional blocks implemented in the DM9101. mii interface 100base-tx transmitter 100base-tx receiver 10base-t tranceiver carrier sense collision detection auto negotiation mii serial management interface figure 1 mii interface the dm 9101 provides a media independent interface (mii) as defined in the ieee 802.3u standard (clause 22). the purpose of the mii interface is to provide a simple, easy to implement connection between the mac recon ciliation layer and the phy. the mii is designed to make the differences between various media transparent to the mac sublayer. the mii consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facil itate data transfers between the phy and the reconciliation layer. ? txd (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to tx_clk. for each tx_clk period which tx_en is asserted, txd (3:0) are accepted for transmission by the phy. ? tx_clk (transmit clock) output to the mac reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the tx_en, txd, and tx_er signals. ? tx_en (transmit enable) input from the mac reconciliation sublayer to indicate nibbles are being presented on the mii for transmission on the physical medium.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 13 version: DM9101-ds-f03 july 22, 1999 ? mii interface (continued) ? tx_er (transmit coding error) tran sitions synchronously with respect to tx_clk. if tx_er is asserted for one or more clock periods, and tx_en is asserted, the phy will emit one or more symbols that are not part of the valid data d elimiter set somewhere in the frame being transmitted. ? rxd (receive data) is a nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to rx_clk. for each rx_clk period which rx_dv is asserted, rxd (3:0) are transferred from the phy to the mac reconciliation sublayer. ? rx_clk (receive clock) output to the mac reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the rx_dv, rxd, and rx_er signals. ? rx_dv (receive data valid) input from the phy to indicate the phy is presenting recovered and dec oded nibbles to the mac reconciliation sublayer. to interpret a receive frame correctly by the reconciliation sublayer, rx_dv must encompass the frame starting no later than the start-of-frame delimiter and excluding any end-stream delimiter. ? rx_er (receive error) tran sitions s ynchr onously with respect to rx_clk. rx_er will be asserted for 1 or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame being transmitted from the phy to the reconciliation sublayer. ? crs (carrier sense) is asserted by the phy when either the transmit or receive m edium is non- idle and deasserted by the phy when the transmit and receive medium are idle. figure 2 depicts the behavior of crs during 10base-t and 100base-tx transmission. txd preamble sfd data efd preamble sfd data esd j/k ssd t/r 10base-t 100base-tx txd crs crs idle idle figure 2
DM9101 10/100mbps ethernet physical layer single chip transceiver 14 final version: DM9101-ds-f03 july 22, 1999 100base-tx operation the 100base-tx transmitter receives 4-bit nibble data clocked in at 25mhz at the mii, and o utputs a sc rambled 5-bit encoded mlt-3 signal to the media at 100mbps. the on-chip clock circuit converts the 25mhz clock into a 125mhz clock for internal use. the ieee 802.3u specification defines the media independent interface. the interface specification defines a dedica ted receive data bus and a dedicated transmit data bus. these two busses incl ude various controls and si gnal indications that facilitate d ata transfers bet ween the DM9101 and the reconciliation layer. 100base-tx transmit the 100base-tx transmitter c onsists of the functional blocks shown in figure 3. the 100base-tx transmit section converts 4-bit synchronous data provi ded by the mii to a scrambled mlt-3 125 million symbols per second serial data stream. transmit mii interface/ control 4b/5b encoder register scrambler parallel to serial nrz to nrzi nrzi to mlt-3 mlt-3 driver rise/fall time ctl tx cgm led driver collision detection carrier sense 10base-t module rx tx led1-4# 25m osci rxi+/- 10txd+/- 100txd+/- txclk txen txd (3:0 txer figure 3
DM9101 10/100mbps ethernet physical layer single chip transceiver final 15 version: DM9101-ds-f03 july 22, 1999 100base-tx operation the block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. the transmitter section contains the following functional blocks: - 4b5b encoder - scrambler - parallel to serial converter - nrz to nrzi converter - nrzi to mlt-3 - mlt-3 driver 4b5b encoder the 4b5b encoder converts 4-bit (4b) nibble data generated by the mac reconciliation layer into a 5-bit (5b) code group for transmission, reference table 1. this conversion is required for control and packet data to be combined in code gr oups. the 4 b5b encoder substitutes the first 8 bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmit. the 4b5b enc oder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of the transmit enable signal from the mac reconciliation layer, the 4b5b encoder injects the t/r code-group pair (01101 00111) indicating end of frame. after the t/r code-group pair, the 4b5b encoder continuously i njects idles into the transmit data stream until transmit enable is asserted and the next transmit packet is detected. the DM9101 includes a bypass 4b5b conversion option within the 100base -tx transmitter for support of applications like 100 mbps repeaters which do not require 4b5b conversion. scrambler the scrambler is required to control the radiated emissions (emi) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100base-tx operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scrambler, energy l evels on the cable could peak beyond fcc limitations at f requencies related to repeated 5b sequences like conti nuous trans mission of idle symbols. the scrambler output is combined with the nrz 5b data from the code-group encoder via an xor logic function. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. parallel to serial converter the parallel to serial conver ter receives parallel 5b scrambled data from the scrambler and serializes it (converts it from a para llel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi encoder block nrz to nrzi encoder after the transmit data stream has been scrambled and serialized, the data must be nrzi encoded for compatibility with the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. mlt-3 converter the mlt-3 conversion is accomplished by converting the data stream output from the nrzi enc oder into two binary data streams with alternately phased logic one events. mlt-3 driver the two binary data streams created at the mlt-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current mlt-3 signal. refer to figure 4 for the block diagram of the mlt-3 converter.
DM9101 10/100mbps ethernet physical layer single chip transceiver 16 final version: DM9101-ds-f03 july 22, 1999 4b5b code group symbol meaning 4b code 3210 5b code 43210 0 data 0 0000 11110 1 data 1 0001 01001 2 data 2 0010 10100 3 data 3 0011 10101 4 data 4 0100 01010 5 data 5 0101 01011 6 data 6 0110 01110 7 data 7 0111 01111 8 data 8 1000 10010 9 data 9 1001 10011 a data a 1010 10110 b data b 1011 10111 c data c 1100 11010 d data d 1101 11011 e data e 1110 11100 f data f 1111 11101 i idle undefined 11111 j sfd (1) 0101 11000 k sfd (2) 0101 10001 t esd (1) undefined 01101 r esd (2) undefined 00111 h error undefined 00100 v invalid undefined 00000 v invalid undefined 00001 v invalid undefined 00010 v invalid undefined 00011 v invalid undefined 00101 v invalid undefined 00110 v invalid undefined 01000 v invalid undefined 01100 v invalid undefined 10000 v invalid undefined 11001 table 1
DM9101 10/100mbps ethernet physical layer single chip transceiver final 17 version: DM9101-ds-f03 july 22, 1999 d ck q q . . binary in common driver binary minus binary plus mlt-3 mlt-3 binary in figure 4 100base-tx receiver the 100base-tx receiver contains several function blocks that convert the scrambled 125mb/s serial data to synchronous 4-bit nibble data that is t hen provi ded to the mii. the receive section contains the following functional blocks: - signal detect - digital adaptive equalization - mlt-3 to binary decoder - clock recovery module - nrzi to nrz decoder - serial to parallel - descrambler - code group alignment - 4b5b decoder signal detect the signal detect function meets the specifications mandated by the a nsi xt12 tp-pmd 100base-tx standards for both voltage thresholds and timing parameters. digital adaptive equalization when transmitting data at high speeds over c opper twisted pair cable, attenuation based on fr equency becomes a concern. in high speed twisted pair signaling, the frequency content of the transmitted si gnal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in si gnal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various c able lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. therefore, the compensation or equalization must be adaptive to ensure proper con ditioning of the received signal independent of the cable len gth. mlt-3 to nrzi decoder the DM9101 decodes the mlt-3 information from the digital adaptive equalizer into nrzi data. the relationship between nrzi and mlt-3 data is shown in figure 4.
DM9101 10/100mbps ethernet physical layer single chip transceiver 18 final version: DM9101-ds-f03 july 22, 1999 clock recovery module the clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the clock recovery module locks onto the data stream and extracts the 125mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz dec oder. nrzi to nrz the transmit data stream is required to be nrzi encoded in for compatibility with the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. this conversion process must be reversed on the receive end. the nrzi to nrz decoder, receives the nrzi data stream from the clock recovery module and converts it to a nrz data stream to be presented to the serial to parallel conversion block. serial to parallel the serial to parallel conver ter receives a serial data stream from the nrzi to nrz converter, and converts the data stream to parallel data to be presented to the descrambler. descrambler because of the scramb ling process r equi red to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the descrambler receives scrambled parallel data streams from the serial to parallel converter, descrambles the data streams, and presents the data streams to the code group alignment block. code group alignment the code group alignment block receives un- aligned 5b data from the descrambler and converts it into 5b code gr oup data. c ode group alignment occurs after the j/k is detected, and subsequent data is aligned on a fixed boundary. 4b5b decoder the 4b5b decoder funct ions as a look-up table that translates incoming 5b code groups into 4b (n ibble) data. when receiving a frame, the first 2 5-bit code groups received are the start-of-frame delimiter (j/k symbols). the j/k symbol pair is stripped and two nibbles of preamble pattern are substituted. the last two code groups are the end-of-frame delimiter (t/r symbols). the t/r symbol pair is also stripped from the nibble presented to the reconciliation layer. 10base-t operation the 10base-t transceiver is ieee 802.3u compliant. when the DM9101 is operating in 10base-t mode, the coding scheme is manchester. data processed for transmit is presented to the mii interface in nibble format, converted to a serial bit stream, then manchester encoded. when receiving, the manchester encoded bit stream is decoded and converted into nibble format for presentation to the mii interface. collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simult aneously. when a collision has been detected, it will be reported by the col signal on the mii interface. collision detection is disabled in full duplex operation. carrier sense carrier sense (crs) is asserted in half-duplex operation during transmission or reception of data. during full-duplex mode, crs is asserted only during receive operations. auto-negotiation the objective of auto-negotia tion is to provide a m eans to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities. it is important to note that auto-negotiation does not test the link segment characteristics. the auto-negotiation function provides a means for a device to advertise supported m odes of operation to a remote link partner, acknowledge the receipt and understanding of common m odes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a segm ent to establish a link at the best common mode of operation. if more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 19 version: DM9101-ds-f03 july 22, 1999 auto-negotiation (continued) auto-negotiation also provides a parallel detection function for devices that do not support the auto- negotiation feature. during parallel detection there is no exchange of configuration infor mation, instead, the receive signal is examined. if it is discovered that the signal matches a technology that the receiving device supports, a connection will be automatically establ ished using that tec hnol ogy. this allows devices that do not support auto- negotiation but support a common m ode of operation to establish a link. mii serial management the mii serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. through this interface it is possible to control and configure multiple phy devices, get status and error information, and determine the t ype and c apabilities of the attached phy device(s). the DM9101 management functions correspond to mii specification for ieee 802.3u-1995 (clause 22) for registers 0 through 6 with vendor-spe cific registers 16,17, and 18. in read/write operation, the management data frame is 64-bits long and starts with 32 c ontiguous logic one bits (preamble) synchronization clock cycles on mdc. the start of frame delimiter (sfd) is indicated by a <01> pattern followed by the operation code (op):<10> indicates read operation and <01> indicates write operation. for read operation, a 2-bit turnaround (ta) filing between register address field and d ata field is prov ided for mdio to avoid contention. following the turnaround time, 16-bit data is read from or written onto management registers. serial management interface the serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the mii interface. the serial control interface consists of mdc (management data clock), and mdi/o (management data input/output) signals. the mdio pin is bi-directional and may be shared by up to 32 devices. management interface - read frame structure 32 "1"s 0110a4a3a0r4r3r0 z 0 idle preamble sfd op code phy address register address turn around data idle read write mdc mdio read d15 d14 d1 d0 // // management interface - write frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 1 0 d15 d14 d1 d0 idle preamble sfd op code phy address register address turn around data idle write mdc mdio write figure 5
DM9101 10/100mbps ethernet physical layer single chip transceiver 20 final version: DM9101-ds-f03 july 22, 1999 register description register address register name description 0 bmcr basic mode control register 1 bmsr basic mode status register 2 phyidr1 phy identifier register #1 3 phyidr2 phy identifier register #2 4 anar auto-negotiation advertisement register 5 anlpar auto-negotiation link partner ability register 6 aner auto-negotiation expansion register 16 dscr davicom specified configuration register 17 dscsr davicom specified configuration/status register 18 10btcsr 10base-t configuration/status register others reserved reserved for future use-do not read/write to these registers key to default in the register description that follows, the default column takes the form: , / where : 1 bit set to logic one 0 bit set to logic zero x no default value (pin#) value latched in from pin # at reset : ro = read only rw = read/write : sc = self clearing p = value permanently set ll = latching low lh = latching high
DM9101 10/100mbps ethernet physical layer single chip transceiver final 21 version: DM9101-ds-f03 july 22, 1999 basic mode control register (bmcr) - register 0 bit bit name default description 0.15 reset 0, rw/sc reset: 1=software reset 0=normal operation when set this bit configures the phy status and control registers to their default states. this bit will return a value of one until the reset process is complete 0.14 loopback 0, rw loopback: loopback control register 1=loopback enabled 0=normal operation when in 100m operation is selected, setting this bit will cause the descrambler to lose synchronization. a 720ms "dead time" will occur before any valid data appears at the mii receive outputs 0.13 speed selection 1, rw speed select: 1=100mbps 0=10mbps link speed may be selected either by this bit or by auto- negotiation if bit 12 of this register is set. when auto- negotiation is enabled, this bit will return auto-negotiation link speed. 0.12 auto-negotiation enable 1, rw auto-negotiation enable: 1= auto-negotiation enabled: 0= auto-negotiation disabled: when auto-negotiation is enabled bits 8 and 13 will contain the auto-negotiation results. when auto-negotiation is disabled bits 8 and 13 will determine the duplex mode and link speed 0.11 power down 0, rw power down: 1=power down 0=normal operation setting this bit will power down the DM9101 with the exception of the crystal oscillator circuit 0.10 isolate (phyad= 00000), rw isolate: 1= isolate 0= normal operation when this bit is set the data path will be isolated from the mii interface. tx_clk, rx_clk, rx_dv, rx_er, rxd[3:0], col and crs will be placed in a high impedance state. the management interface is not effected by this bit. when the phy address is set to 00000 the isolate bit will be set upon power-up/reset
DM9101 10/100mbps ethernet physical layer single chip transceiver 22 final version: DM9101-ds-f03 july 22, 1999 basic mode control register (bmcr) - register 0 (continued) bit bit name default description 0.9 restart auto- negotiation 0,rw/sc restart auto-negotiation: 1= restart auto-negotiation. 0= normal operation when this bit is set the auto-negotiation proc ess is re -init iated. when auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and will re turn a value of 1 until auto- negotiation is initiated. the operation of the auto-negotiation process will not be affected by the m anage ment entity that clears this bit 0.8 duplex mode 1,rw duplex mode: 1= full duplex operation. 0= normal operation if auto-negotiation is disabled, setting this bit will cause the DM9101 to operate in full duplex mode. when auto-negotiation is enabled, this bit reflects the duplex selected by auto- negotiation 0.7 collision test 0,rw collision test: 1= collision test enabled. 0= normal operation when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en 0.6 reserved 0,ro reserved: write as 0, ignore on read basic mode status register (bmsr) - register 1 bit bit name default description 1.15 100base-t4 0,ro/p 100base-t4 capable: 1=DM9101 is able to perform in 100base-t4 mode 0=DM9101 is not able to perform in 100base-t4 mode 1.14 100base-tx full duplex 1,ro/p 100base-tx full duplex capable: 1= DM9101 is able to perform 100base-tx in full duplex mode 0= DM9101 is not able to perform 100base-tx in full d uplex mode 1.13 100base-tx half duplex 1,ro/p 100base-tx half duplex capable: 1=DM9101 is able to perform 100base-tx in half d uplex mode 0=DM9101 is not able to perform 100base-tx in half duplex mode 1.12 10base-t full duplex 1,ro/p 10base-t full duplex capable: 1=DM9101 is able to perform 10base-t in full d uplex mode 0=DM9101 is not able to perform 10base-t in full duplex mode 1.11 10base-t half duplex 1,ro/p 10base-t half duplex capable: 1=DM9101 is able to perform 10base-t in half d uplex mode 0=DM9101 is not able to perform 10base-t in half duplex mode. 1.10-1.7 reserved 0,ro reserved: write as 0, ignore on read
DM9101 10/100mbps ethernet physical layer single chip transceiver final 23 version: DM9101-ds-f03 july 22, 1999 basic mode status register (bmsr) - register 1 (continued) bit bit name default description 1.6 mf preamble suppression 0,ro mii frame preamble suppression: 1=phy will accept management frames with pr eamble suppressed 0=phy will not accept management frames with pr eamble suppressed 1.5 auto-negotiation complete 0,ro auto-negotiation complete: 1=auto-negotiation process comp leted 0=auto-negotiation process not comp leted 1.4 remote fault 0, ro/lh remote fault: 1= remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection met hod is dm 9101 i mplementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0= no remote fault condition detected 1.3 auto-negotiation ability 1,ro/p auto configuration ability: 1=DM9101 able to perform auto- negotiation 0=DM9101 not able to perform auto- negotiation 1.2 link status 0,ro/ll link status: 1=valid link established (for either 10mbps or 100mbps operation) 0=link not established the link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain c leared until it is r ead via the manage ment i nterface 1.1 jabber detect 0, ro/lh jabber detect: 1=jabber condition detected 0=no jabber condition detected this bit is implemented with a latching function. once jabber conditions are dete cted this bit will remain set until a read operation is completed through a management interface or a dm 9101 reset. this bit works only in 10mbps mode 1.0 extended capability 1,ro/p extended capability: 1=extended register capable 0=basic register capable only phy id identifier register #1 (phyidr1) - register 2 the phy identifier registers #1 and #2 work together in a single identifier of the dm 9101. the i dentifier c onsists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit bit name default description 2.15-2.0 oui_msb <0181h> oui most significant bits: this register stores bits 3 - 18 of the oui (00606e) to bits 15 - 0 of this register respectively. the m ost significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2)
DM9101 10/100mbps ethernet physical layer single chip transceiver 24 final version: DM9101-ds-f03 july 22, 1999 phy identifier register #2 (phyidr2) - register 3 bit bit name default description 3.15-3.10 oui_lsb <101110>,ro/p oui least significant bits: bits 19 - 24 of the oui (00606e) are mapped to bits 15 - 10 of this register respectively 3.9-3.4 vndr_mdl <000000>,ro/p vendor model number: six bits of the vendor model number mapped to bits 9 - 4 (most significant bit to bit 9) 3.3-3.0 mdl_rev <0010>,ro/p model revision number: four bits of the vendor model revision number mapped to bits 3 - 0 (most significant bit to bit 3) auto-negotiation advertisement register (anar) - register 4 this register contains the advertised abilities of the dm 9101 device as they will be transmitted to link partners during auto- negotiation. bit bit name default description 4.15 np 0,ro/p next page indication: 0=no next page available 1=next page available the DM9101 does not support the next page function. this bit is permanently set to 0 4.14 ack 0,ro acknowledge: 1=link partner ability data reception acknowledged 0=not acknowledged the DM9101's auto-negotiation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the a uto- negotiat ion process. software should not attempt to write to this bit. 4.13 rf 0, rw remote fault: 1=local device senses a fault condition 0=no fault detected 4.12-4.11 reserved x, rw reserved: write as 0, ignore on read 4.10 fcs 0, rw flow control support: 1=controller chip supports flow control ability 0=controller chip doesn?t support flow control ability 4.9 t4 0, ro/p 100base-t4 support: 1=100base-t4 supported by the local device 0=100base-t4 not supported the DM9101 does not support 100base-t4 so this bit is permanently set to 0 4.8 tx_fdx 1, rw 100base-tx full duplex support: 1=100base-tx full duplex supported by the local device 0=100base-tx full duplex not supported 4.7 tx_hdx 1, rw 100base-tx support: 1=100base-tx supported by the local device 0=100base-tx not supported
DM9101 10/100mbps ethernet physical layer single chip transceiver final 25 version: DM9101-ds-f03 july 22, 1999 auto-negotiation advertisement register (anar) - register 4 (continued) bit bit name default description 4.6 10_fdx 1, rw 10base-t full duplex support: 1=10base-t full duplex supported by the local device 0=10base-t full duplex not supported 4.5 10_hdx 1, rw 10base-t support: 1=10base-t supported by the local device 0=10base-t not supported 4.4-4.0 selector <00001>, rw protocol selection bits: these bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports ieee 802.3 csma/cd. auto-negotiation link partner ability register (anlpar) - register 5 this register contains the advertised abilities of the link partner as they are received during auto- negoti ation. bit bit name default description 5.15 np 0, ro next page indication: 0= link partner, no next page avai lable 1= link partner, next page available 5.14 ack 0, ro acknowledge: 1=link partner ability data reception acknowledged 0=not acknowledged the DM9101's auto-negotiation state machine will automatically control this bit from the incoming flp bur sts. software should not attempt to write to this bit. 5.13 rf 0, ro remote fault: 1=remote fault indicated by link partner 0=no remote fault indicated by link partner 5.12-5.10 reserved x, ro reserved: write as 0, ignore on read 5.9 t4 0, ro 100base-t4 support: 1=100base-t4 supported by the link partner 0=100base-t4 not supported by the link partner 5.8 tx_fdx 0, ro 100base-tx full duplex support: 1=100base-tx full duplex supported by the link partner 0=100base-tx full duplex not supported by the link partner 5.7 tx_hdx 0, ro 100base-tx support: 1=100base-tx half duplex supported by the link partner 0=100base-tx half duplex not supported by the link partner 5.6 10_fdx 0, ro 10base-t full duplex support: 1=10base-t full duplex supported by the link partner 0=10base-t full duplex not supported by the link partner 5.5 10_hdx 0, ro 10base-t support: 1=10base-t half duplex supported by the link partner 0=10base-t half duplex not supported by the link partner 5.4-5.0 selector <00000>, ro protocol selection bits: link partner binary encoded protocol selector
DM9101 10/100mbps ethernet physical layer single chip transceiver 26 final version: DM9101-ds-f03 july 22, 1999 auto-negotiation expansion register (aner) - register 6 bit bit name default description 6.15-6.5 reserved x, ro reserved: write as 0, ignore on read 6.4 pdf 0, ro/lh local device parallel detection fault: pdf=1: a fault detected via parallel detection function. pdf=0: no fault detected via parallel detection function 6.3 lp_np_able 0, ro link partner next page able: lp_np_able=1: link partner, next page available lp_np_able=0: link partner, no next page 6.2 np_able 0,ro/p local device next page able: np_able=1: DM9101, next page available np_able=0: DM9101, no next page DM9101 does not support this function, so this bit is always 0. 6.1 page_rx 0, ro/lh new page received: a new link code word page received. this bit will be automatically cleared when the register (register 6) is read by management. 6.0 lp_an_able 0, ro link partner auto-negotiation able: lp_an_able=1 indicates that the link partner supports auto- negotiation. davicom specified configuration register (dscr) - register 16 bit bit name default description 16.15 bp_4b5b pin96, rw bypass 4b5b enc oding and 5b4b decoding: 1=4b5b encoder and 5b4b decoder function bypassed 0=normal 4b5b and 5b4b operation the value of the pin is latched into this bit at power-up/reset. 16.14 bp_scr pin97, rw bypass scrambler/descrambler function: 1=scrambler and descrambler function bypassed 0=normal scrambler and descrambler operation the value of the input pin is lat ched into this bit at power- up/reset. 16.13 bp_align pin95, rw bypass symbol alignment function: 1= receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions (symbol encoder and scrambler) bypassed 0= normal operation the value of the bpalign input pin is lat ched into this bit at power-up/reset. 16.12 reserved 0, rw reserved: this bit must be set as 0.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 27 version: DM9101-ds-f03 july 22, 1999 davicom specified configuration register (dscr) - register 16 (continued) bit bit name default description 16.11 repeater 0, rw repeater/node mode: 1=repeater mode 0=node mode in repeater mode, the carrier sense (crs) output from the DM9101 will be asserted only by receive activity. in node mode, or a mode not configured for full duplex operation, crs will be asserted by either receive or transmit activity. the value of the rptr/node input pin is lat ched into this bit at power-up reset. 16.10 tx 1, rw 100base-tx or fx mode control: 1=100base-tx operation 0=100base-fx operation 16.9 utp 1, rw utp cable control: 1=the media is a utp cable, 0=stp 16.8 clk25mdis 0, rw clk25m disable: 1=clk25m output clock signal tri-stated 0=clk25m enabled this bit should be set to 1 to disable the 25mhz output and reduce ground bounce and power consumption. for applications requiring the clk25m output, set this bit to 0. 16.7 f_link_100 0, rw force good link in 100mbps: 0=normal 100mbps operation 1=force 100mbps good link status this bit is useful for diagnostic purposes. 16.6 reserved 1, rw reserved: 16.5 linkled_ctl 0, rw linkled mode select: 0= link led output configured to indicate link status only 1= link led output configured to indicate traffic status: when the link status is ok, the led will be on. when the chip is in transmitting or receiving, it flashes. 16.4 fdxled_mode 0, rw fdxled mode select: 1= fdxled output configured to indicate polarity in 10base-t mode 0= fdxled output configured to indicate full duplex mode status for 10mbps and 100mbps operation 16.3 smrst 0, rw reset state machine: when this bit is set to 1, all state internal machines will be reset. this bit will clear after reset is completed. 16.2 mfpsc 0, rw mf preamble suppression control: 1= mf preamble suppression on 0= mf preamble suppression off mii frame preamble suppression control bit
DM9101 10/100mbps ethernet physical layer single chip transceiver 28 final version: DM9101-ds-f03 july 22, 1999 davicom specified configuration register (dscr) - register 16 (continued) bit bit name default description 16.1 sleep 0, rw sleep mode: writing a 1 to this bit will cause DM9101 to enter sleep mode and power down all circuits except the oscillator and clock generator circuit. to exit sleep mode, write 0 to this bit position. the prior configuration will be re tained when the sl eep s tate is terminated, but the state machine will be reset 16.0 rlout 0, rw remote loopout control: when this bit is set to 1, the received data will l oop out to the transmit channel. this is useful for bit error rate testing davicom specified configuration and status register (dscsr) - register 17 bit bit name default description 17.15 100fdx 1, ro 100m full duplex operation: after auto-negotiation is completed, the results will be written to this bit. a ?1? in this bit position indicates 100m full duplex operation. the software can read b its [15:12] to determine which mode is selected after auto-negotiation. this bit is invalid when auto-negotiation is disabled. 17.14 100hdx 1, ro 100m half duplex operation: after auto-negotiation is completed, the results will be written to this bit. a ?1? in this bit position indicates 100m half duplex operation. the software can read b its [15:12] to determine which mode is selected after auto-negotiation. this bit is invalid when auto-negotiation is disabled. 17.13 10fdx 1, ro 10m full duplex operation: after auto-negotiation is completed, the results will be written to this bit. a ?1? in this bit position indicates 10m full duplex operation. the software can read b its [15:12] to determine which mode is selected after auto-negotiation. this bit is invalid when auto-negotiation is disabled. 17.12 10hdx 1, ro 10m half duplex operation: after auto-negotiation is completed, the results will be written to this bit. a ?1? in this bit position indicates 10m half duplex operation. the software can read b its [15:12] to determine which mode is selected after auto-negotiation. this bit is invalid when auto-negotiation is disabled. 17.11- 17.10 reserved 0, rw reserved: write as 0, ignore on read 17.8-17.4 phyad[4:0] (phyad), rw phy address bit 4:0: the values of the phyad[4:0] pins are latched to this register at power-up/reset. the first phy address bit transmitted or received is the msb (bit 4). a station management entity connected to multiple phy entities must know the appropriate address of each phy. a phy address of <00000> will cause the isolate bit of the bmcr (bit 10, register address 00) to be set.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 29 version: DM9101-ds-f03 july 22, 1999 davicom specified configuration and status register (dscsr) - register 17 (continued) bit bit name default description 17.3-17.0 anmb[3:0] 0, ro auto-negotiation monitor bits: these bits are for debug only. the auto- negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 0 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0 1 0 0 consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detect signal_link_ready 0 1 1 1 parallel detect signal_link_ready fail 1 0 0 0 auto-negotiation completed successfully 10base-t configuration/status (10btcsrcsr) - register 18 bit bit name default description 18.15 reserved 0, ro reserved: write as 0, ignore on read 18.14 lp_en 1, rw link pulse enable: 1=transmission of link pulses enabled 0=link pulses disabled, good link condition forced this bit is valid only in 10mbps operation. 18.13 hbe (inverse pin94),rw heartbeat enable: 1=heartbeat function enabled 0=heartbeat function disabled when the DM9101 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode). the initial state of this bit is the inverse value of rptr/node input pin at power on reset. 18.12 reserved 0, ro reserved: write as 0, ignore on read 18.11 jaben 1, rw jabber enable: 1= jabber function enabled 0= jabber function disabled enables or disables the jabber function when the DM9101 is in 10base-t full duplex or 10base-t transceiver loop-back mode 18.10 10bt_ser pin98, rw 10base-t serial mode: 1=10base-t serial mode selected 0=10base-t nibble mode selected the value on the 10btser input pin is latched into this bit at power-up/reset serial mode not supported for 100mbps operation. 18.9-18.1 reserved 0, ro reserved: write as 0, ignore on read
DM9101 10/100mbps ethernet physical layer single chip transceiver 30 final version: DM9101-ds-f03 july 22, 1999 10base-t configuration/status (10btcsrcsr) - register 18 (continued) bit bit name default description 18.0 polr 0, ro polarity reversed: when this bit is set to 1, it indicates that the 10m cable polarity is reversed. this bit is set and cleared by 10base-t module automatically. absolute maximum ratings* operating voltage (vcc) 4.75v to 5.25v non-operating voltage (vcc) -0.5v to 7.00v dc input voltage (vin) -0.5v to vcc +0.5v dc output voltage (vout) -0.5v to vcc +0.5v storage temperature range (tstg) -65 to +150 operating ambient temperature range 0 to 70 lead temp (tl) (soldering 10 sec.) 235 esd rating (rzap=1.5k, czap=100pf) 4000v power consumption: 100base-tx full duplex 185 ma (measured using unscrambled idle trans miss ion looped back to rxin, includes external termination circuitry) 10base-t full d uplex 222 ma (measured using maximum packet size, minimum i.p.g. transmission looped back to r xin, incl udes ex ternal termination circuitry). power consumption: (continued) auto-negotiation 165ma (measured during pa rallel d etect until link establis hed) idle 120ma (measured with no link established) power down mode 40ma (measured while mii register 0 bit 11 set true) *comments stresses above those listed under ?absolute maximum ratings? may cause per manent dam age to the device. these are stress ratings only. functional operation of this device at these or any other con ditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliab ility.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 31 version: DM9101-ds-f03 july 22, 1999 dc electrical characteristics (vcc = 5vdc, 5%, ta = 0 to 70, unless spe cified otherwise) symbol parameter min. typ. max. unit conditions i 100tx supply c urrent 100base-tx active 180 185 ma v cc = 5.0v i 10ttp supply current 10base-tx active (random data, random ipg and random size) 120 ma v cc = 5.0v i 10twc supply current 10base-tx active (max. packet size, min. ipg and worst case data patern) 220 ma v cc = 5.0v i pdm supply current power down mode 40 ma v cc = 5.0v i an supply c urrent during auto-neg. 165 ma v cc = 5.0v i rst supply c urrent during reset. 115 ma v cc = 5.0v ttl inputs (txd0-txd3, tx_clk, mdio, tx_en, tx_dv, tx_er, testmode, phyad0-4, opmode0-4, rptr, bpalign, bp4b5b, bpscr, 10btser, reset# ) v il input low voltage 0.8 v i il = -400ua v ih input high voltage 2.0 v i ih = 100ua i il input low current -200 ua v in = 0.4v i ih input high current 100 ua v in = 2.7v mii ttl outputs ( rxd0-3, rx_en, rx_dv, rx_er, crs, col, mdio ) v ol output low voltage 0.4 v i ol = 4ma v oh output high voltage 2.4 v i oh = -4ma non-mii ttl outputs (txled#, rxled#, linkled#, colled#, fdxled#, rx_lock) v ol output low voltage 0.4 v i ol = 1ma v oh output high voltage 2.4 v i oh = -0.1ma receiver v icm rxi+/rxi- input common-mode voltage 1.5 2.0 2.5 v 100 ? termination across transmitter itd100 100txo+/- 100base-tx mode differential output current 19 21 ma itd10 10tx+/- 10base-t differential output current 44 50 56 ma
DM9101 10/100mbps ethernet physical layer single chip transceiver 32 final version: DM9101-ds-f03 july 22, 1999 ac electrical characteristics (over full range of operating condition unless spe cified otherwise) symbol parameter min. typ. max. unit conditions transmitter t tr/f 100txo+/- differential rise/fall time 3.0 5.0 ns t tm 100txo+/- differential rise/fall time mismatch -0.5 0.5 ns t tdc 100txo+/- differential output duty cycle distortion -0.5 0.5 ns t t/t 100txo+/- differential output peak-to-peak jitter 300 ps xost 100txo+/- differential voltage overshoot 5% mii (media-independent interface) xntol tx input clock frequency tolerance ppm 25mhz frequency xbtol tx output clock frequency tolerance -100 +100 ppm 25mhz frequency t pwh osc pulse width high 14 ns t pw l osc pulse width low 14 ns t rpwh rx_clk pulse width high 14 ns t rpwl rx_clk pulse width low 14 ns
DM9101 10/100mbps ethernet physical layer single chip transceiver final 33 version: DM9101-ds-f03 july 22, 1999 mii-100base-tx transmit timing diagram tx_clk t tx h t 2 t tx s t 1 t tx pd t tx r/f txd [0:3], tx_en, tx_er crs 100tx+/- mii-100base-tx transmit timing parameters (half duplex) symbol parameter min. typ 1 . max. unit conditions t tx s txd[0:3], tx_en, tx_er setup to tx_clk high 11 - - ns t tx h txd[0:3], tx_en, tx_er hold from tx_clk high 0- -ns t 1 tx_en sampled to crs asserted -4-bt t 2 tx_en sampled to crs de- asserted -4-bt t tx pd tx_en sampled to tpo out (tx latency) -8-bt t tx r/f 100tx driver rise/fall time 3 4 5 ns 90% to 10%, into 100ohm differential 1 . typical values are at 25 and are for design aid only; not guaranteed and not subject to pr oduction testing. mii-100base-tx receive timing diagram rx_clk t 2 t 1 t tx pd rxd [0:3], rx_dv, rx_er crs rxi+/- t rx s t rx h t 4 t 3 col t 5
DM9101 10/100mbps ethernet physical layer single chip transceiver 34 final version: DM9101-ds-f03 july 22, 1999 mii-100base-tx receive timing parameter (half duplex) symbol parameter min. typ 1 . max. unit conditions t rx s rxd[0:3), rx_dv, rx_er setup to rx_clk high 10 - - ns t rx h rxd[0:3], rx_dv, rx_er hold from rx_clk high 10 - - ns t rx pd rxi in to rxd[0:3] out (rx latency) -15-bt t 1 crs asserted to rx d[0:3], rx_dv, rx_er -4-bt t 2 crs de-asserted to rxd[0:3], rx_dv, rx_er -0-bt t 3 rxi in to crs asserted 10 - 14 bt t 4 rxi quiet to crs de-asserted 14 - 18 bt t 5 rxi in to col de-asserted 14 - 18 bt 1 . typical values are at 25and are for design aid only; not guaranteed and not subject to pr oduction testing. auto-negotiation and fast link pulse timing diagram fast link pulses clock pulse data pulse clock pulse t 1 t 2 t 3 flp burst flp burst t 4 t 5 10tx0+/- auto-negotiation and fast link pulse timing parameters symbol parameter min. typ. max. unit conditions t 1 clock/data pulse width - 100 - ns t 2 clock pulse to data pulse period - 62.5 - us data = 1 t 3 clock pulse to clock pulse period - 125 - us t 4 flp burst width - 2 - ms t 5 flp burst to flp burst period - 13.93 - ms - clock/data pulses per burst 33 33 33 ea
DM9101 10/100mbps ethernet physical layer single chip transceiver final 35 version: DM9101-ds-f03 july 22, 1999 mii-10base-t nibble transmit timing diagram tx_clk t tx h t 2 t tx s t 1 t tx pd txd [0:3], tx_en, tx_er crs 10tx+/- mii-10base-t nibble transmit timing parameters symbol parameter min. typ. max. unit conditions t tx s txd[0:3), tx_en, tx_er setup to tx_clk high 11 - - ns t tx h txd[0:3], tx_en, tx_er hold from tx_clk high 0--ns t 1 tx_en sampled to crs asserted -24bt t 2 tx_en sampled to crs de- asserted -1520bt t tx pd tx_en sampled to 10txo out (tx latency) -24bt mii-10base-t receive nibble timing diagram rx_clk t 2 t 1 t tx pd rxd [0:3], rx_dv, rx_er crs rxi+/- t rx s t rx h t 4 t 3
DM9101 10/100mbps ethernet physical layer single chip transceiver 36 final version: DM9101-ds-f03 july 22, 1999 mii-10base-t receive nibble timing parameters symbol parameter min. typ. max. unit conditions t rx s rxd[0:3), rx_dv, rx_er setup to rx_clk high 10 - - ns t rx h rxd[0:3], rx_dv, rx_er hold from rx_clk high 10 - - ns t rx pd rxi in to rxd[0:3] out (rx latency) -7-bt t 1 crs asserted to rx d[0:3], rx_dv, rx_er 11420bt t 2 crs de-asserted to rxd[0:3], rx_dv, rx_er --3bt t 3 rxi in to crs asserted 1 2 4 bt t 4 rxi quiet to crs de-asserted 1 10 15 bt 10base-t sqe (heartbeat) timing diagram tx_clk tx_en col t 1 t 2 10base-t sqe (heartbeat) timing parameters symbol parameter min. typ. max. unit conditions t 1 col (sqe) delay after tx_en off 0.65 1.3 1.6 ms t 2 col (sqe) pulse duration 0.5 1.1 1.5 ms 10base-t jab and unjab timing diagram tx_en t 2 t 1 tdx col
DM9101 10/100mbps ethernet physical layer single chip transceiver final 37 version: DM9101-ds-f03 july 22, 1999 10base-t jab and unjab timing parameters symbol parameter min. typ. max. unit conditions t 1 maximum transmit time 20 48 150 ms t 2 unjab time 250 505 1500 ms mdio timing when output by sta mdc t 1 mdio 10ns (min) t 2 10ns (min) mdio timing when output by DM9101 mdc t 3 mdio 0 - 300 ns mii timing parameters symbol parameter min. typ. max. unit conditions t 1 mdio setup before mdc 10 - - ns when output by sta t 2 mdio hold after mdc 10 - - ns when output by sta t 3 mdc to mdio output delay 0 - 100 ns when outptu by DM9101
DM9101 10/100mbps ethernet physical layer single chip transceiver 38 final version: DM9101-ds-f03 july 22, 1999 magnetics selection guide the DM9101 requires a 1:1 ratio for both the receive and the transmit transformers. refer to table 2 for transformer requirements. transformers meeting these requirements are available from a variety of magnetic manufacturers. designers should test and qualify all magnetics before using them in an applic ation. the transformers listed in table 2 are electrical equivalent, but may not be pin-to-pin equivalent. manufacturer part number bel fuse s558-5999-01 delta lf8200, lf8221 fil-mag pt41715 halo tg22-3506nd, td22-3506g1, tg22-s010nd tg22-s012nd nano pulse inc. npi 6181-37, npi 6120-30, npi 6120-37 npi 6170-30 pulse engineering pe-68517, pe-68515, h1019, h1012 ----single port h1027, h1028 ---- dual port pe-69037, h1001, h1036, h1044 ---- quad port valor st6114, st6118 ycl 20pmt04, 20pmt05 table 2 crystal selection guide a crystal can be used to generate the 25mhz reference clock instead of a crystal oscillator. an m-tron crystal, part number is 00301-00169, mp-1 fund, @ 25.000000mhz, 50ppm or equivalent may be used. the crystal must be a f undamental type, parallel resonant. connect to x1 and x2, shunt each crystal lead to ground with an 18pf capacitor (see figure 6). 29 30 x2 x1 32 31 osc/xtlb oscgnd agnd agnd agnd c18 18pf y1 25m c19 18pf figure 6 crystal circuit diagram
DM9101 10/100mbps ethernet physical layer single chip transceiver final 39 version: DM9101-ds-f03 july 22, 1999 item no. qty. reference number part description 1 11 c1,c2,c3,c4,c5,c6,c7,c8,c9, c10,c11 capacitor, decoupling, 0.1uf, 50v 2 1 c12 capacitor,.01uf,2kv 3 4 d1,d2,d3,d4 led, general purpose 4 1 j1 connector, rj45 5 1 l1 ferrite, panasonicexccl4532u 6 1 osc1 oscillator, crystal, 25mhz, 50ppm 7 2 q2,q1 transistor, nnp, general purpose, 2n2222 8 2 r1,r2 resistor, 470 ? , 5% 9 1 r3 resistor, 820 ? , 5% 10 1 r4 resistor, 33 ? , 5% 11 1 r5 resistor, 510 ? , 5% 12 1 r6 resistor, 6.01k ? , 1% 13 4 r7,r8,r14,r15 resistor, 49.9 ? , 1% 14 1 r9 resistor, 1.5k ? , 5% 15 4 r10,r11,r12,r13 resistor, 75 ? , 1% 16 2 r17,r16 resistor, 10k ? , 5% 17 1 u1 DM9101f, phy/transceiver, 100pin qfp 18 1 u2 magnetics, pulse engineering, pe68515 table 3 parts list for example design table 3 is a list of materials used in the design example shown on the next page. where a specific v endor name has been called out, the designer can substitute an equivalent part.
DM9101 10/100mbps ethernet physical layer single chip transceiver 40 final version: DM9101-ds-f03 july 22, 1999 decoupling for vcc decoupling for vcc mii interface DM9101 mii example schematic gnd gnd vcc vcc vcc chassis gnd gnd gnd gnd vcc gnd gnd c11 .01u/2kv r5 510 r15 49.9 1% d2 fdx led q2 2n2222 r4 33 u1 DM9101f avcc 1 nc 2 nc 3 nc 4 nc 5 agnd 6 avcc 7 avcc 8 rxi- 9 rxi+ 10 agnd 11 agnd 12 10txo- 13 10txo+ 14 avcc 15 avcc 16 agnd 17 agnd 18 nc 19 nc 20 avcc 21 avcc 22 agnd 23 agnd 24 100txo- 25 100txo+ 26 avcc 27 avcc 28 osci/x1 29 x2 30 avcc 33 agnd 34 bgres 35 bggnd 36 dgnd 37 dgnd 38 dgnd 39 dvcc 40 tridrv 41 utp 42 speed10 43 rx_lock 44 dgnd 45 nc 46 linksts 47 clk25m 48 dvcc 49 fdxled# 50 colled# 51 dgnd 52 linkled# 53 rxled# 54 txled# 55 tx_er/txd4 56 txd3 57 txd2 58 txd1 59 txd0 60 dgnd 61 dvcc 62 tx_en 63 tx_clk 64 mdc 65 mdio 66 dgnd 67 dvcc 68 rxd3 69 rxd2 70 rxd1 71 rxd0 72 dgnd 73 dvcc 74 rx_clk 75 crs 76 col 77 rx_dv 78 rx_er/rxd4 79 rx_en 80 reset# 81 testmode 82 phyad0 83 phyad1 84 phyad2 85 dgnd 86 dvcc 87 phyad3 88 phyad4 89 opmode0 90 opmode1 91 opmode2 92 opmode3 93 rptr/node# 94 bpalign 95 bp4b5b 96 bpscr 97 10btser 98 osc/xtl# 32 agnd 99 agnd 100 agnd 31 c1 .1u r17 10k osc1 25mhz out 8 nc 1 gnd 7 +vdd 14 r12 75 1% r3 820 r7 49.9 1% c6 .1u r13 75 1% c12 .1u c8 .1u r8 49.9 1% r14 49.9 1% c10 .1u d4 10m led c2 .1u c3 .1u c5 .1u r16 10k r10 75 1% c7 .1u l1 26 x1 pe68515 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 d1 act led r2 470 d3 100m led r6 6.01k 1% r1 470 r11 75 1% c4 .1u q1 2n2222 c9 .1u j1 rj45 1 2 3 4 5 6 7 8 r9 1.5k txd2 txd0 txd1 rx_dv rxd1 rx_clk tx_en gnd rx_er gpio7 tx_clk rx_en tx_er rxd2 col rxd0 mdio /reset txd3 rxd3 vcc crs mdc
DM9101 10/100mbps ethernet physical layer single chip transceiver final 41 version: DM9101-ds-f03 july 22, 1999 package information lqfp 100l outline dimensions unit: inches/mm l g d ~ ~ ~ l 1 detail f c a 1 a 2 a seating plane g d see detail f h d d e h e f d y 51 75 50 26 76 100 b 125 e symbol dimensions in inches dimensions in mm a 0.063 max. 1.60 max. a 1 0.004 0.002 0.1 0.05 a 2 0.055 0.002 1.40 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.15 0.05 d 0.551 0.005 14.00 0.13 e 0.551 0.005 14.00 0.13 e 0.020 bsc. 0.50 bsc. f 0.481 nom. 12.22 nom. g d 0.606 nom. 15.40 nom. h d 0.630 0.006 16.00 0.15 h e 0.630 0.006 16.00 0.15 l 0.024 0.006 0.60 0.15 l 1 0.039 ref. 1.00 ref. y 0.004 max. 0.1 max. 0 ~ 12 0 ~ 12 notes: 1. dimension d & e do not include resin fins. 2. dimension gd is for pc board surface mount pad pitch design reference only. 3. all dimensions are based on metric system.
DM9101 10/100mbps ethernet physical layer single chip transceiver 42 final version: DM9101-ds-f03 july 22, 1999 package information qfp 100l outline dimensions unit: inches/mm b e a 1 a 2 a seating plane 1 30 31 50 51 80 81 100 h d d f e h e g e g d see detail f d y l g d ~ ~ ~ l 1 detail f c symbol dimensions in inches dimensions in mm a 0.130 max. 3.30 max. a 1 0.004 min. 0.10 min. a 2 0.1120.005 2.850.13 b0.012 +0.004 0.31 +0.10 -0.002 -0.05 c0.006 +0.004 0.15 +0.10 -0.002 -0.05 d 0.5510.005 14.000.13 e 0.7870.005 20.000.13 e 0.026 0.006 0.650.15 f 0.742 nom. 18.85 nom. g d 0.693 nom. 17.60 nom. g e 0.929 nom. 23.60 nom. h d 0.7400.012 18.800.31 h e 0.9760.012 24.790.31 l 0.0470.008 1.190.20 l 1 0.0950.008 2.410.20 y 0.006 max. 0.15 max. 0 ~ 12 0 ~ 12 note: 1. dimension d & e do not include resin fins. 2. dimension gd & ge are for pc board surface mount pad pitch design reference only. 3. all dimensions are based on metric system.
DM9101 10/100mbps ethernet physical layer single chip transceiver final 43 version: DM9101-ds-f03 july 22, 1999 ordering information part number pin count package DM9101e 100 lqfp DM9101f 100 qfp disclaimer the information appea ring in this publica tion is believed to be accur ate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipu lated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the informa tion in this publication or regarding the freedom of the descri bed chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. da vicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the r eader is cauti oned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliab ility requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor, inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic pr oducts that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compat ible with major hardware and software standards. our currently available and soon to be released pr oducts are ba sed on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters: hsin-chu office: 4f, no. 17, park avenue ii, science-based park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-8797 fax: 886-3-579-8858 taipei sales office: 8f, no. 3, lane 235, bao-chiao road, hsin-tien city, taipei, taiwan, r.o.c. tel: 886-2-2915-3030 fax: 886-2-2915-7575 email: sales@davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/o r function.

▲Up To Search▲

Price & Availability of DM9101

	To Download DM9101 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .